1. Field of the Invention
The present invention relates to an image forming apparatus and a control method thereof configured to convert print data into raster image data to form an image.
2. Description of the Related Art
In recent years, creating document data using a PC (personal computer) has become common practice. Accordingly, many printing apparatuses such as copiers, facsimiles, printers and the like are now provided with a PDL printing function that interprets PDL data generated by an application executed on a PC and renders print data such as PDL data into raster image data to be printed. Such a PDL data (print data) rendering process is primarily performed by software executed by a CPU (central processing unit) of the printing apparatus. In addition, there is a demand for increasing the rendering speed of such PDL data in order to further improve the printing speed of the printing apparatus.
A conceivable method of increasing the processing speed of a CPU is to increase the clock frequency of a CPU clock that drives the CPU. However, an increase of clock frequency results in an increase of electric power consumption of the CPU and the higher the printing speed of a printing apparatus, the greater the electric power consumption. Consequently, there is a problem in that an increase of the clock frequency of a CPU in combination with the high-speed performance of a printing apparatus further increases total electric power consumption.
Meanwhile, in mobile devices such as a notebook PC or the like, reducing electric power consumption by dynamically changing the clock frequency of a CPU has become common practice. Similarly, with printing systems, techniques for dynamically changing the clock frequency of a CPU that executes a PDL data rendering process are described in Japanese Patent Laid-Open No. 2003-345567 and Japanese Patent Laid-Open No. 2003-94773.
According to a multifunction system described in Japanese Patent Laid-Open No. 2003-345567, a processing load of a PDL data rendering process is predicted according to the amount of PDL data or the type of application that generated the PDL data. Furthermore, in a case that the load of a PDL data rendering process is predicted to be large, the processing capability for PDL data rendering is increased by increasing the clock frequency of the CPU. Japanese Patent Laid-Open No. 2003-345567 also describes that an increase in overall electric power consumption is suppressed by prohibiting concurrent activation of other jobs upon increasing the clock frequency of the CPU.
According to a print system described in Japanese Patent Laid-Open No. 2003-94773, a time period required to print PDL data is measured and recorded per processing unit (1 page or 1 band), whereby processing speed is increased by increasing the clock frequency of CPU when the required time period is lengthened.
The technique described in Japanese Patent Laid-Open No. 2003-345567 requires that a load of a PDL data rendering process be predicted in advance. However, it is difficult to accurately predict the load of a PDL data rendering process from the data amount of the PDL data or the application that generated the PDL data. Therefore, in the event of a prediction failure, a situation occurs where PDL data with a large load is processed by a CPU driven by a CPU clock with a low frequency, resulting in a significant increase in processing time. In addition, when restricting concurrent operations by the printing apparatus in order to suppress increases in total electric power consumption, there is a problem of operability degradation.
Furthermore, with the technique disclosed in Japanese Patent Laid-Open No. 2003-94773, a processing time period of a performed printing process of PDL data is measured per processing unit, and a clock frequency of the CPU for processing a next processing unit is determined based on the measured processing time period. Therefore, when the load changes drastically from one processing unit to the next, there is a risk that processing performance will actually decline. Moreover, an increase in electric power consumption due to an increase in the clock frequency of a CPU is not considered. However, since power consumption is restricted in a real-world apparatus, in all actuality, the clock frequency cannot be increased beyond a certain level.